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RT8283A 1 ds8283a-01 march 2011 www.richtek.com ordering information note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. applications wireless ap/router set-top-box industrial and commercial low power systems lcd monitors and tvs green electronics/appliances point of load regulation of high-performance dsps 3a, 23v, 340khz synchronous step-down converter general description the RT8283A is a high efficiency, monolithic synchronous step-down dc/dc converter that can deliver up to 3a output current from a 4.5v to 23v input supply. the RT8283A's current mode architecture and external compensation allow the transient response to be optimized over a wide range of loads and output capacitors. cycle-by-cycle current limit provides protection against shorted outputs and soft-start eliminates input current surge during start-up. the RT8283A also provides output under voltage protection and thermal shutdown protection. the low current (<3 a) shutdown mode provides output disconnect, enabling easy power management in battery- powered systems. the RT8283A is available in a sop-8 (exposed pad) package. features 1.5% high accuracy feedback voltage 4.5v to 23v input voltage range 3a output current integrated n-mosfet switches current mode control fixed frequency operation : 340khz output adjustable from 0.8v to 20v up to 95% efficiency programmable soft-start stable with low-esr ceramic output capacitors cycle-by-cycle over current protection input under voltage lockout output under voltage protection thermal shutdown protection rohs compliant and halogen free pin configurations (top view) sop-8 (expoaed pad) boot vin sw gnd ss en fb comp gnd 2 3 4 5 6 7 8 9 marking information RT8283Agsp : product number x : h or l ymdnn : date code RT8283A xgspymdnn package type sp : sop-8 (exposed pad-option 1) RT8283A lead plating system g : green (halogen free and pb free) h : uvp hiccup l : uvp latch-off
RT8283A 2 ds8283a-01 march 2011 www.richtek.com functional pin description pin no. pin name pin function 1 boot bootstrap for high side gate driver. connect a 0.1 f or greater ceramic capacitor from boot to sw pins. 2 vin input supply voltage, 4.5v to 23v. must bypass with a suitably large ceramic capacitor. 3 sw phase node--connect to external l-c filter.. 4, 9 (exposed pad) gnd ground. the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation. 5 fb feedback input pin. this pin is connected to the converter output. it is used to set the output of the converter to regulate to the desired value via an internal resistive divider. for an adjustable output, an external resistive divider is connected to this pin. 6 comp compensation node. comp is used to compensate the regulation control loop. connect a series rc network from comp to gnd. in some cases, an additional capacitor from comp to gnd is required. 7 en enable input pin. a logic high enables the converter; a logic low forces the rt8253a into shutdown mode reducing the supply current to less than 3 a. attach this pin to vin with a 100k pull up resistor for automatic startup. 8 ss soft-start control input. ss controls the soft-start period. connect a capacitor from ss to gnd to set the soft-start period. a 0.1 f capacitor sets the soft-start period to 13.5ms. v out (v) r1 (k ) r2 (k ) r c (k ) c c (nf) l ( h) c out ( f) 8 27 3 33 3.3 22 22 x 2 5 62 11.8 20 3.3 15 22 x 2 3.3 75 24 13 3.3 10 22 x 2 2.5 25.5 12 9.1 3.3 6.8 22 x 2 1.5 10.5 12 5.6 3.3 3.6 22 x 2 1.2 12 24 4.3 3.3 3.6 22 x 2 1 3 12 3.6 3.3 2 22 x 2 recommended component selection typical application circuit vin en gnd boot sw 7 2 3 1 l 10h 100nf 22f x 2 r1 75k r2 24k v out 3.3v/3a 10f x 2 v in 4.5v to 23v RT8283A ss 8 c ss 4, 9 (exposed pad) c boot c in 0.1f c out r en 100k comp c c 3.3nf r c 13k c p open 6 fb 5
RT8283A 3 ds8283a-01 march 2011 www.richtek.com function block diagram va + - + - + - uv comparator oscillator foldback control 0.4v internal regulator + - 2.7v shutdown comparator current sense amplifier boot vin gnd sw fb en comp 3v 5k va v cc 6a slope comp current comparator + - ea 0.8v s r q q ss + - 1.2v lockout comparator v cc + 85m 85m
RT8283A 4 ds8283a-01 march 2011 www.richtek.com electrical characteristics (v in = 12v, t a = 25 c, unless otherwise specified) absolute maximum ratings (note 1) supply voltage, v in -------------------------------------------------------------------------------------------------- ? 0.3v to 25v input v oltage, sw ---------------------------------------------------------------------------------------------------- ? 0.3v to (v in + 0.3v) v boot ? v sw ----------------------------------------------------------------------------------------------------------- ? 0.3v to 6v other pins voltage --------------------------------------------------------------------------------------------------- ? 0.3v to 6v power dissipation, p d @ t a = 25 c sop-8 (exposed pad) ---------------------------------------------------------------------------------------------- 1.333w package thermal resistance (note 2) sop-8 (exposed pad), ja ----------------------------------------------------------------------------------------- 75 c/w sop-8 ( xposed pad), jc ---------------------------------------------------------------------------------------- 15 c/w lead temperature (soldering, 10 sec.) ----------------------------------- --------------------------------------- 260 c junction temperature ------------------------------------------------------------------------------------------------ 150 c storage temperature range --------------------------------------------------------------------------------------- ? 40 c to 150 c esd susceptibility (note 3) hbm (human body mode) ----------------------------------------------------------------------------------------- 2kv mm (ma chine mode) ------------------------------------------------------------------------------------------------- 200v recommended operating conditions (note 4) supply voltage, v in -------------------------------------------------------------------------------------------------- 4.5v to 23v junction temperature range --------------------------------------------------------------------------------------- ? 40 c to 125 c ambient temperature range --------------------------------------------------------------------------------------- ? 40 c to 85 c parameter symbol test conditions min typ max unit shutdown supply current v en = 0v -- 0.5 3 a supply current v en = 3 v, v fb = 0.9v -- 0.8 1.2 ma feedback voltage v fb 4.5v v in 23v 0.788 0.8 0.812 v error amplifier transconductance gea ic = 10 a -- 940 -- a/v high side switch on-resistance r ds(on)1 -- 85 -- m low side switch on-resistance r ds(on)2 -- 85 -- m high side switch leakage current v en = 0v, v sw = 0v -- 0 10 a upper switch current limit min. duty c ycle, v boot ? v sw = 4.8v 4.5 5.8 -- a lower switch current limit from drain to source -- 1.5 -- a comp to current sense transconductance g cs -- 5.6 -- a/v oscillation frequency f osc1 300 340 380 khz short circuit oscillation frequency f osc2 v fb = 0v -- 110 -- khz maximum duty cycle d max v fb = 0.7v -- 93 -- % minimum on time t on -- 100 -- ns to be continued
RT8283A 5 ds8283a-01 march 2011 www.richtek.com parameter symbol test conditions min typ max unit logic high v ih 2.7 -- 5.5 en threshold voltage logic low v il -- -- 0.4 v input under voltage lockout threshold v in rising 3.8 4.2 4.5 v input under voltage lockout threshold hysteresis -- 320 -- mv soft-start current v ss = 0v -- 6 -- a soft-start period c ss = 0.1 f -- 13.5 -- ms thermal shutdown t sd -- 150 -- c note 1. stresses listed as the above " absolute maximum ratings " may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. ja is measured in the natural convection at t a = 25 c on a high effective thermal conductivity four layers test board of jedec 51-7 thermal measurement standard. the case point of jc is on the expose pad for sop-8 (exposed pad) package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions.
RT8283A 6 ds8283a-01 march 2011 www.richtek.com frequency vs. temperature 300 310 320 330 340 350 360 370 380 -50 -25 0 25 50 75 100 125 temperature (c) frequency (khz) 1 reference voltage vs. temperature 0.780 0.785 0.790 0.795 0.800 0.805 0.810 0.815 0.820 -50 -25 0 25 50 75 100 125 temperature (c) reference voltage (v) efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 0 0.5 1 1.5 2 2.5 3 output current (a) efficiency (%) reference voltage vs. input voltage 0.780 0.785 0.790 0.795 0.800 0.805 0.810 0.815 0.820 4 6 8 1012141618202224 input voltage (v) reference voltage (v) output voltage vs. output current 3.24 3.26 3.28 3.30 3.32 3.34 3.36 00.511.522.53 output current (a) output voltage (v) frequency vs. input voltage 300 310 320 330 340 350 360 370 380 4 6 8 1012141618202224 input voltage (v) frequency (khz) 1 typical operating characteristics v out = 3.3v v in = 4.5v v in = 12v v in = 23v v in = 4.5v to 23v, v out = 3.3v, i out = 0a v in = 12v v out = 3.3v, i out = 0a v in = 4.5v v in = 12v v in = 23v v out = 3.3v, i out = 0a v in = 12v, v out = 3.3v, i out = 0a
RT8283A 7 ds8283a-01 march 2011 www.richtek.com current limit vs. duty cycle 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 0 102030405060708090100 duty cycle (%) current limit (a) current limit vs. temperature 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 -50 -25 0 25 50 75 100 125 temprature (c) current limit (a) v in = 4.5v to 23v, v out = 3.3v v in = 12v, v out = 3.3v load transient response time (100 s/div) v out (200mv/div) i out (2a/div) v in = 12v, v out = 3.3v, i out = 0a to 3a switching time (1 s/div) v out (10mv/div) i l (2a/div) v in = 12v, v out = 3.3v, i out = 3a v sw (10v/div) load transient response time (100 s/div) v out (200mv/div) i out (2a/div) v in = 12v, v out = 3.3v, i out = 1.5a to 3a switching time (1 s/div) v out (10mv/div) i l (2a/div) v in = 12v, v out = 3.3v, i out = 1.5a v sw (10v/div)
RT8283A 8 ds8283a-01 march 2011 www.richtek.com power on from v in time (5ms/div) v out (2v/div) i l (2a/div) v in = 12v, v out = 3.3v, i out = 3a v in (5v/div) power on from en time (5ms/div) v out (2v/div) i l (2a/div) v in = 12v, v out = 3.3v, i out = 3a v en (5v/div) power off from en time (5ms/div) v out (2v/div) i l (2a/div) v in = 12v, v out = 3.3v, i out = 3a v en (5v/div) power off from v in time (5ms/div) v out (2v/div) i l (2a/div) v in = 12v, v out = 3.3v, i out = 3a v in (5v/div)
RT8283A 9 ds8283a-01 march 2011 www.richtek.com application information the RT8283A is a synchronous high voltage buck converter that can support the input voltage range from 4.5v to 23v and the output current can be up to 3a. output voltage setting the resistive divider allows the fb pin to sense the output voltage as shown in figure 1. figure 1. output voltage setting the output voltage is set by an external resistive voltage divider according to the following equation : ?? + ?? ?? out fb r1 v = v1 r2 where v fb is the feedback reference voltage (0.8v typ.). external bootstrap diode connect a 100nf low esr ceramic capacitor between the boot pin and sw pin. this capacitor provides the gate driver voltage for the high side mosfet. it is recommended to add an external bootstrap diode between an external 5v and boot pin for efficiency improvement when input voltage is lower than 5.5v or duty ratio is higher than 65% .the bootstrap diode can be a low cost one such as in4148 or bat54. the external 5v can be a 5v fixed input from system or a 5v output of the RT8283A. note that the external boot voltage must be lower than 5.5v figure 2. external bootstrap diode soft-start the RT8283A contains an external soft-start clamp that gradually raises the output voltage. the soft-start timming can be programed by the external capacitor between ss pin and gnd. the chip provides a 6 a charge current for the external capacitor. if 0.1 f capacitor is used to set the soft-start, it's period will be 13.5ms(typ.). chip enable operation the en pin is the chip enable input. pulling the en pin low (<0.4v) will shutdown the device. during shutdown mode, the RT8283A quiescent current drops to lower than 3 a. driving the en pin high (>2.7v, < 5.5v) will turn on the device again. for external timing control (e.g.rc), the en pin can also be externally pulled high by adding a r en * resistor and c en * capacitor from the vin pin (see figure 5). an external mosfet can be added to implement digital control on the en pin when no system voltage above 2.5v is available, as shown in figure 3. in this case, a 100k pull-up resistor, r en , is connected between v in and the en pin. mosfet q1 will be under logic control to pull down the en pin. RT8283A gnd fb r1 r2 v out sw boot 5v RT8283A 100nf vin en gnd boot fb sw 7 5 2 3 1 l r1 r2 v out chip enable v in rt8284 ss 8 c ss comp c c r c c p 6 4, 9 (exposed pad) c boot c out c in r en q1 100k figure 3. enable control circuit for logic control with low voltage to prevent enabling circuit when v in is smaller than the v out target value, a resistive voltage divider can be placed between the input voltage and ground and connected to the en pin to adjust ic lockout threshold, as shown in figure 4. for example, if an 8v output voltage is regulated from a 12v input voltage, the resistor r en2 can be selected to set input lockout threshold larger than 8v.
RT8283A 10 ds8283a-01 march 2011 www.richtek.com out in rms out(max) in out v v i = i 1 vv ? this formula has a maximum at v in = 2v out , where i rms = i out / 2. this simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. for the input capacitor,two 10 f low esr ceramic capacitors are recommended. for the recommended capacitor, please refer to table 3 for more detail. the selection of c out is determined by the required esr to minimize voltage ripple. moreover, the amount of bulk capacitance is also a key for c out selection to ensure that the control loop is stable. loop stability can be checked by viewing the load transient response as described in a later section. c in and c out selection the input capacitance, c in, is needed to filter the trapezoidal current at the source of the high side mosfet. to prevent large ripple current, a low esr input capacitor sized for the maximum rms current should be used. the rms current is given by : table 2. suggested inductors for typical application circuit component supplier series dimensions (mm) tdk vlf10045 10 x 9.7 x 4.5 tdk slf12565 12.5 x 12.5 x 6.5 taiyo yuden nr8040 8 x 8 x 4 having a lower ripple current reduces not only the esr losses in the output capacitors but also the output voltage ripple. high frequency with small ripple current can achieve highest efficiency operation. however, it requires a large inductor to achieve this goal. for the ripple current selection, the val ue of i l = 0.24(i max ) will be a reasonable starting point. the large st ripple current occurs at the highest v in . to guarantee that the out out l(max) in(max) vv l = 1 fi v ??? ? ? ??? ? ??? ? the inductor's current rating (caused a 40 c temperature rising from 25 c ambient) should be greater than the maximum load current and its saturation current should be greater than the short circuit peak current limit. please see table 2 for the inductor selection reference. out out l in vv i = 1 fl v ??? ? ?? ??? ? ??? ? under voltage protection hiccup mode for the RT8283Ah, it provides hiccup mode under voltage protection (uvp). when the fb voltage drops below half of the feedback reference voltage, v fb , the uvp function will be triggered and the RT8283Ah will shut down for a period of time and then recover automatically. the hiccup mode uvp can reduce input current in short-circuit conditions. latch-off mode for the RT8283Al, it provides latch-off mode under voltage protection (uvp). when the fb voltage drops below half of the feedback reference voltage, v fb , uvp will be triggered and the RT8283Al will shutdown in latch- off mode. in shutdown condition, the RT8283Al can be reset by en pin or power input vin. inductor selection the inductor value and operating frequency determine the ripple current according to a specific input and output voltage. the ripple current i l increases with higher v in and decreases with higher inductance. figure 4. the resistors can be selected to set ic lockout threshold vin en gnd boot fb sw 7 5 2 3 1 l r1 r2 v out v in RT8283A ss 8 c ss comp c c r c c p 6 4, 9 (exposed pad) c boot c out c in 100k 8v 12v r en2 r en1 10f ripple current stays below the specified maximum, the inductor value should be chosen according to the following equation :
RT8283A 11 ds8283a-01 march 2011 www.richtek.com out l out 1 viesr 8fc ?? ?? + ?? ?? the output ripple will be highest at the maximum input voltage since i l increases with input voltage. multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirement. dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. special polymer capacitors offer very low esr value. however, it provides lower capacitance density than other types. although tantalum capacitors have the highest capacitance density, it is important to only use types that pass the surge test for use in switching power supplies. aluminum electrolytic capacitors have significantly higher esr. however, it can be used in cost-sensitive applications for ripple current rating and long term reliability considerations. ceramic capacitors have excellent low esr characteristics but can have a high voltage coefficient and audible piezoelectric effects. the high q of ceramic capacitors with trace inductance can also lead to significant ringing. higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. their high ripple current, high voltage rating and low esr make them ideal for switching regulator applications. however, care must be taken when these capacitors are used at input and output. when a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, v in . at best, this ringing can couple to the output and be mistaken as loop instability. at worst, a sudden the output ripple, v out , is determined by : inrush of current through the long wires can potentially cause a voltage spike at v in large enough to damage the part. checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to i load (esr) also begins to charge or discharge c out generating a feedback error signal for the regulator to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability problem. emi consideration since parasitic inductance and capacitance effects in pcb circuitry w ould cause a spike voltage on sw pin when high side mosfet is turned-on /off, this spike voltage on sw may impact on emi performance in the system. in order to enhance emi performance, there are two methods to suppress the spike voltage. one is to place an r-c snubber between sw and gnd and make them as close as possible to the sw pin (see figure 5). another method is adding a resistor in series with the bootstrap capacitor, c boot . but this method will decrease the driv ing capability to the high side mosfet. it is strongly recommended to reserve the r-c snubber during pcb layout for emi improvement. moreover, reducing the sw trace area and keeping the main power in a small loop will be helpful on emi performance. for detailed pcb layout guide, please refer to the section of layout consideration. figure 5. reference circuit with snubber and enable timing control vin en gnd boot fb sw 7 5 2 3 1 l 10h 100nf 22fx2 r1 75k r2 24k v out 3.3v/3a 10f x 2 chip enable v in 4.5v to 23v RT8283A ss 8 c ss 0.1f comp c c 3.3nf r c 13k c p nc 6 4, 9 (exposed pad) c boot c out c in r boot * r s * c s * r en * c en * * : optional
RT8283A 12 ds8283a-01 march 2011 www.richtek.com (a) copper area = (2.3 x 2.3) mm 2 , ja = 75 c/w (b) copper area = 10mm 2 , ja = 64 c/w (c) copper area = 30mm 2 , ja = 54 c/w figure 7. derating curves for RT8283A package 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 0 255075100125 ambient temperature p ower di ss i pat i on (w) ( c) copper area 70mm 2 50mm 2 30mm 2 10mm 2 min.layout four layer pcb thermal considerations for continuous operation, do not exceed the maximum operation junction temperature 125 c . the maximum power dissipation depends on the thermal resistance of ic package, pcb layout, the rate of surroundings airflow and temperature difference between junction to ambient. the maximum power dissipation can be calculated by following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum operation junction temperature , t a is the ambient temperature and the ja is the junction to ambient thermal resistance. for recommended operating conditions specification of RT8283A, the maximum junction temperature is 125 c . the junction to ambient thermal resistance ja is layout dependent. for psop-8 package, the thermal resistance ja is 75 c /w on the standard jedec 51-7 four-layers thermal test board. the maximum power dissipation at t a = 25 c can be calculated by following formula : p d(max) = (125 c ? 25 c ) / (75 c /w) = 1.333w (min.copper area pcb layout) p d(max) = (125 c ? 25 c ) / (49 c /w) = 2.04w (70mm 2 copper area pcb layout) the thermal resistance ja of sop-8 (exposed pad) is determined by the package architecture design and the pcb layout design. however, the package architecture design had been designed. if possible, it's useful to increase thermal performance by the pcb layout copper design. the thermal resistance ja can be decreased by adding copper area under the exposed pad of sop-8 (ex posed pad) package. as shown in figure 6, the amount of copper area to which the sop-8 (exposed pad) is mounted affects thermal performance. when mounted to the standard sop-8 (exposed pad) pad (figure 6.a), ja is 75 c/w. adding copper area of pad under the sop-8 (exposed pad) (figure 6.b) reduces the ja to 64 c/w. even further, increasing the copper area of pad to 70mm 2 (figure 6.e) reduces the ja to 49 c/w. the maximum power dissipation depends on operating ambient temperature for fixed t j (max) and thermal resistance ja . for RT8283A packages, the figure 7 of derating curves allows the designer to see the effect of rising ambient temperature on the maximum power dissipation allowed.
RT8283A 13 ds8283a-01 march 2011 www.richtek.com (d) copper area = 50mm 2 , ja = 51 c/w (e) copper area = 70mm 2 , ja = 49 c/w figure 6. themal resistance vs. copper area layout design layout consideration follow the pcb layout guidelines for optimal performance of the RT8283A. ` keep the traces of the main current paths as short and wide as possible. ` put the input capacitor as close as possible to the device pins (vin and gnd). ` lx node is with high frequency voltage swing and should be kept at small area. keep analog components away from the lx node to prevent stray capacitive noise pick- up. ` connect feedback network behind the output capacitors. keep the loop area small. place the feedback components near the RT8283A. ` connect all analog grounds to a command node and then connect the command node to the power ground behind the output capacitors. ` an example of pcb layout guide is shown in figure 6 for reference. figure 8. pcb layout guide v in v out gnd c in gnd c p c c r c sw v out c out l1 r1 r2 input capacitor must be placed as close to the ic as possible. sw should be connec ted to inductor by wide and short trace. keep sensitive components away from this trace. the feedback components must be connected as close to the device as possible. boot vin sw gnd ss en fb comp gnd 2 3 4 5 6 7 8 9 c s r s * c s * gnd v in r en
RT8283A 14 ds8283a-01 march 2011 www.richtek.com table 3. suggested capacitors for c in and c out location component supplier part no. capacitance (uf) case size c in murata grm31cr61e106k 10 1206 c in tdk c3225x5r1e106k 10 1206 c in taiyo yuden tmk316bj106ml 10 1206 c out murata grm31cr60j476m 47 1206 c out tdk c3225x5r0j476m 47 1210 c out murata grm32er71c226m 22 1210 c out tdk c3225x5r1c22m 22 1210
RT8283A 15 ds8283a-01 march 2011 www.richtek.com information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property inf ringement of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications i s assumed by richtek. richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 richtek technology corporation taipei office (marketing) 5f, no. 95, minchiuan road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)86672399 fax: (8862)86672377 email: marketing@richtek.com outline dimension a b j f h m c d i y x exposed thermal pad (bottom of package) 8-lead sop (exposed pad) plastic package symbol dimensions in millimeters dimensions in inches min max min max a 4.801 5.004 0.189 0.197 b 3.810 4.000 0.150 0.157 c 1.346 1.753 0.053 0.069 d 0.330 0.510 0.013 0.020 f 1.194 1.346 0.047 0.053 h 0.170 0.254 0.007 0.010 i 0.000 0.152 0.000 0.006 j 5.791 6.200 0.228 0.244 m 0.406 1.270 0.016 0.050 option 1 x 2.000 2.300 0.079 0.091 y 2.000 2.300 0.079 0.091 option 2 x 2.100 2.500 0.083 0.098 y 3.000 3.500 0.118 0.138

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